added configuration and better handeling of UART line endings

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0xRoM / glitch-o-bolt

Browse code added configuration and better handeling of UART line endings master
1 parent d145fd2 commit f7be3c63c73350c40e32d5452d320956e2909e76 root authored 5 days ago

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Ignore Space Show notes View ConfigDemoAll.py

Ignore Space Show notes View FaultycatModules/__pycache__/ConfigBoard.cpython-310.pyc 0 → 100644
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Ignore Space Show notes View FaultycatModules/__pycache__/UART.cpython-310.pyc 0 → 100644
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Ignore Space Show notes View FaultycatModules/__pycache__/Worker.cpython-310.pyc 0 → 100644
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Ignore Space Show notes View __pycache__/ConfigBaudBrute.cpython-310.pyc 0 → 100644
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Ignore Space Show notes View __pycache__/functions.cpython-310.pyc 0 → 100644
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Ignore Space Show notes View __pycache__/scope.cpython-310.pyc 0 → 100644
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Ignore Space Show notes View functions.py

Ignore Space Show notes View glitch-o-bolt.py

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