Ross Marks

Fork: 0

0xRoM / PiPins

Browse code correct naming? master
1 parent 23ffcce commit bace5b35a9ff25be91687c412a17bb4282c727cb root authored on 16 Mar 2020

Patch

Unified Split

Showing 2 changed files

                Show notes
              View
            
          
          24 ■■■■■
          logic_analyser.txt
        
        
          100644 → 0
              - Logic Analyzer - PulseView -
 
The serial connection is available on the PC (running Linux) as /dev/ttyUSB0. The sniffer is started using sigrok-cli, and the resulting sigrok session data is opened with PulseView.
 
Command given on PC:
 
sigrok-cli --driver=ols:conn=/dev/ttyUSB0 --config samplerate=3000000 --samples 100000 --probes 1=CLK,2=DIN,3=DC,4=nCS,5=nRST --triggers nCS=1 -o test.sr
--driver: The sniffer identifies itself as a Open Bench Logic Sniffer (OLS) on port /dev/ttyUSB0
--config samplerate: using the maximum of 3M samples/s
--samples: 100000 samples (taking ~33ms at 3 MHz)
--probes: probe 1-5 are used, the labels are optional
--triggers: the sampling starts after probe 4 (nCS, inverted chip select) turns high
-o test.sr: the session is saved to a file that can be read by PulseView
The probes relate to the GPIO ports of the PI as:
SUMP probe	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15
Rev 1 GPIO	7	8	11	9	25	10	24	23	22	21	18	17	17	17	17	17
Rev 2 GPIO	7	8	11	9	25	10	24	23	22	27	18	17	28	29	30	31
This gives 12 probes on the rev1 board, 16 probes on rev 2 (if using the P5 header).
The I2C and GPIO clock pins are reserved for future use.
 
possibly better logic analyzer for the pi:
https://github.com/richardghirst/Panalyzer
"The basic idea is that it disables interrupts for a period, while sampling the GPIO pins once a microsecond.  It then re-enables interupts and displays traces showing what the relevant GPIO pins were doing."
- - Logic Analyzer - PulseView -
-The serial connection is available on the PC (running Linux) as /dev/ttyUSB0. The sniffer is started using sigrok-cli, and the resulting sigrok session data is opened with PulseView.
-Command given on PC:
-sigrok-cli --driver=ols:conn=/dev/ttyUSB0 --config samplerate=3000000 --samples 100000 --probes 1=CLK,2=DIN,3=DC,4=nCS,5=nRST --triggers nCS=1 -o test.sr
---driver: The sniffer identifies itself as a Open Bench Logic Sniffer (OLS) on port /dev/ttyUSB0
---config samplerate: using the maximum of 3M samples/s
---samples: 100000 samples (taking ~33ms at 3 MHz)
---probes: probe 1-5 are used, the labels are optional
---triggers: the sampling starts after probe 4 (nCS, inverted chip select) turns high
--o test.sr: the session is saved to a file that can be read by PulseView
-The probes relate to the GPIO ports of the PI as:
-SUMP probe	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15
-Rev 1 GPIO	7	8	11	9	25	10	24	23	22	21	18	17	17	17	17	17
-Rev 2 GPIO	7	8	11	9	25	10	24	23	22	27	18	17	28	29	30	31
-This gives 12 probes on the rev1 board, 16 probes on rev 2 (if using the P5 header).
-The I2C and GPIO clock pins are reserved for future use.
-possibly better logic analyzer for the pi:
-https://github.com/richardghirst/Panalyzer
-"The basic idea is that it disables interrupts for a period, while sampling the GPIO pins once a microsecond.  It then re-enables interupts and displays traces showing what the relevant GPIO pins were doing."

                Ignore Space
               Show notes
              View
            
          
          24 ■■■■■
          logic_analyzer.txt
        
        
        
          0 → 100644
              - Logic Analyzer - PulseView -
 
The serial connection is available on the PC (running Linux) as /dev/ttyUSB0. The sniffer is started using sigrok-cli, and the resulting sigrok session data is opened with PulseView.
 
Command given on PC:
 
sigrok-cli --driver=ols:conn=/dev/ttyUSB0 --config samplerate=3000000 --samples 100000 --probes 1=CLK,2=DIN,3=DC,4=nCS,5=nRST --triggers nCS=1 -o test.sr
--driver: The sniffer identifies itself as a Open Bench Logic Sniffer (OLS) on port /dev/ttyUSB0
--config samplerate: using the maximum of 3M samples/s
--samples: 100000 samples (taking ~33ms at 3 MHz)
--probes: probe 1-5 are used, the labels are optional
--triggers: the sampling starts after probe 4 (nCS, inverted chip select) turns high
-o test.sr: the session is saved to a file that can be read by PulseView
The probes relate to the GPIO ports of the PI as:
SUMP probe	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15
Rev 1 GPIO	7	8	11	9	25	10	24	23	22	21	18	17	17	17	17	17
Rev 2 GPIO	7	8	11	9	25	10	24	23	22	27	18	17	28	29	30	31
This gives 12 probes on the rev1 board, 16 probes on rev 2 (if using the P5 header).
The I2C and GPIO clock pins are reserved for future use.
 
possibly better logic analyzer for the pi:
https://github.com/richardghirst/Panalyzer
"The basic idea is that it disables interrupts for a period, while sampling the GPIO pins once a microsecond.  It then re-enables interupts and displays traces showing what the relevant GPIO pins were doing."
+ - Logic Analyzer - PulseView -
+The serial connection is available on the PC (running Linux) as /dev/ttyUSB0. The sniffer is started using sigrok-cli, and the resulting sigrok session data is opened with PulseView.
+Command given on PC:
+sigrok-cli --driver=ols:conn=/dev/ttyUSB0 --config samplerate=3000000 --samples 100000 --probes 1=CLK,2=DIN,3=DC,4=nCS,5=nRST --triggers nCS=1 -o test.sr
+--driver: The sniffer identifies itself as a Open Bench Logic Sniffer (OLS) on port /dev/ttyUSB0
+--config samplerate: using the maximum of 3M samples/s
+--samples: 100000 samples (taking ~33ms at 3 MHz)
+--probes: probe 1-5 are used, the labels are optional
+--triggers: the sampling starts after probe 4 (nCS, inverted chip select) turns high
+-o test.sr: the session is saved to a file that can be read by PulseView
+The probes relate to the GPIO ports of the PI as:
+SUMP probe	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15
+Rev 1 GPIO	7	8	11	9	25	10	24	23	22	21	18	17	17	17	17	17
+Rev 2 GPIO	7	8	11	9	25	10	24	23	22	27	18	17	28	29	30	31
+This gives 12 probes on the rev1 board, 16 probes on rev 2 (if using the P5 header).
+The I2C and GPIO clock pins are reserved for future use.
+possibly better logic analyzer for the pi:
+https://github.com/richardghirst/Panalyzer
+"The basic idea is that it disables interrupts for a period, while sampling the GPIO pins once a microsecond.  It then re-enables interupts and displays traces showing what the relevant GPIO pins were doing."

Show line notes below